| Opcode |
Operation |
Z |
C |
N |
V |
Notes |
| adc[cond][s] Rd, Rn, <sh_op> |
Rd = Rn + <s_op> + C |
s |
s |
s |
s |
|
| add[cond][s] Rd, Rn, <sh_op> |
Rd = Rn + <s_op> |
s |
s |
s |
s |
|
| and[cond][s] Rd, Rn, <sh_op> |
Rd = Rn & <s_op> |
s |
s |
s |
|
|
| b[cond] <target_addr> |
PC = PC + <offset> |
|
|
|
|
|
| bic[cond][s] Rd, Rn, <sh_op> |
Rd = Rn & !<s_op> |
s |
s |
s |
|
|
| bl[cond] <target_addr> |
LR = PC+4; PC = PC + <offset> |
|
|
|
|
|
| bx[cond] Rm |
PC = Rm; Mode=THUMB |
s |
s |
s |
|
|
| cmn[cond] Rn, <sh_op> |
<flags> = Rn + <s_op> |
x |
x |
x |
x |
|
| cmp[cond] Rn, <sh_op> |
<flags> = Rn - <s_op> |
x |
x |
x |
x |
|
| eor[cond][s] Rd, Rn, <sh_op> |
Rd = xor_bits(Rn,<s_op>) |
s |
s |
s |
|
|
| ldr[cond] Rd, Rn, # |
Rd = [Rn + #] |
|
|
|
|
word |
| ldr[cond]B Rd, Rn, # |
Rd = [Rn + #] |
|
|
|
|
byte |
| ldr[cond]BT Rd, Rn, # |
Rd = [Rn + #] |
|
|
|
|
translate byte |
| ldr[cond]H Rd, <address> |
Rd = [address] |
|
|
|
|
half word |
| ldr[cond]SB Rd, <address> |
Rd = [address] |
|
|
|
|
signed byte |
| ldr[cond]SH Rd, <address> |
Rd = [address] |
|
|
|
|
signed half word |
| ldr[cond]T Rd, Rn, # |
Rd = [Rn + #] |
|
|
|
|
translate word |
| mov[cond][s] Rd, <sh_op> |
Rd = <s_op> |
s |
s |
s |
|
|
| mul[cond][s] Rd, Rm, Rs |
Rd = Rm * Rs |
s |
s |
s |
|
|
| mvn[cond][s] Rd, <sh_op> |
Rd = -<s_op> |
s |
s |
s |
|
|
| orr[cond][s] Rd, Rn, <sh_op> |
Rd = or_bits(Rn,<s_op>) |
s |
s |
s |
|
|
| rsb[cond][s] Rd, Rn, <sh_op> |
Rd = <s_op> - Rn |
s |
s |
s |
s |
(==neg) |
| rsc[cond][s] Rd, Rn, <sh_op> |
Rd = <s_op> - Rn + C |
s |
s |
s |
s |
|
| sbc[cond][s] Rd, Rn, <sh_op> |
Rd = Rn - <s_op> + C |
s |
s |
s |
s |
|
| smlal[cond][s] RdLo, RdHi, Rm, Rs |
RdHi RdLo = Rm*Rs+(RdHi RdLo) |
s |
s |
s |
s |
64bit target |
| smull[cond][s] RdLo, RdHi, Rm, Rs |
RdHi RdLo = Rm*Rs |
s |
s |
s |
s |
64bit target |
| stm[cond]<adm> Rm<!>, {reglst} |
[Rm+=4] = for each in <reglist> |
|
|
|
|
"!" Keeps last Rm Value |
| stm[cond]<adm> Rm<!>, {reglst}^ |
special, see doc |
|
|
|
|
|
| str[cond] Rd, Rn, # |
[Rn + #] = Rd |
|
|
|
|
word |
| str[cond]B Rd, Rn, # |
[Rn + #] = Rd |
|
|
|
|
byte |
| str[cond]BT Rd, Rn, # |
[Rn + #] = Rd |
|
|
|
|
translate byte |
| str[cond]H Rd, <address> |
[address] = Rd |
|
|
|
|
half word |
| str[cond]T Rd, Rn, # |
[Rn + #] = Rd |
|
|
|
|
translate word |
| sub[cond][s] Rd, Rn, <sh_op> |
Rd = Rn - <s_op> |
s |
s |
s |
s |
|
| swi <swi_number> |
call software interrupt |
|
|
|
|
|
| swp[cond] Rd, Rm, [Rn] |
Rd = [Rn]; [Rn] = Rm |
|
|
|
|
|
| swp[cond]B Rd, Rm, [Rn] |
Rd = [Rn]; [Rn] = Rm |
|
|
|
|
|
| teq[cond] Rn, <sh_op> |
<flags> = xor_bits(Rn,<s_op>) |
x |
x |
x |
|
|
| tst[cond] Rn, <sh_op> |
<flags> = and_bits(Rn,<s_op>) |
x |
x |
x |
|
|
| Flag |
Description |
| Z |
Zero Flag |
| C |
Carry Flag |
| N |
Negative Flag |
| V |
Overflow Flag |
Note there are no specific masks for the Z/C/N/V bits, since they are part of the CSPR register and while there
are 16 condition codes and 16 possible flag states there is no direct correspondance between them, for instance
eq triggers on half of all possible flag states, rather than just one of them. In fact V and Z masks do exist,
but they refer to other bits of the instruction.
Flag settings:
s - if flag set
x - always
* - special
