ARM supported opcodes
Note the following table does not contain anything from ARM fpu.
Also, "lea Rn,[var]" is (usually) encoded as mov/orr (Phix-specific).
The five main shift operations (asl/asr/lsl/lsr/ror) are just shorthands for the equivalent mov instruction with that operation embedded via the barrel shifter.
There is no difference whatsoever between asl and lsl, and in fact they use the same encoding.
Note that (the Phix-specific aliases) shl and shr must be unconditional, if used, ditto lea.
Phix does not support or permit the use of r11..r15 as (confusing) aliases for important registers.
| Mnemonic | Description | Phix-specific and standard aliases |
| adc | Add with Carry | |
| add | Add | |
| and | Logical and_bits | |
| b | Branch | jmp (unconditional) |
| bic | Bit Clear | or , not (unconditional) |
| bl | Branch and Link | call (unconditional) |
| bx | Branch and Exchange | ret ( === bx lr, unconditional) |
| cmn | Compare Negative | cmp -ve imm is standard |
| cmp | Compare | |
| eor | Logical Exclusive or_bits | xor (unconditional) |
| ldm | Load Multiple | pop is standard |
| ldr | Load Register | mov Rn, [Rm|fp+k] |
| mla | Multiply Accumulate | |
| mov | Move | lsl, asl, shl, lsr, shr, asr, ror |
| mul | Multiply | |
| mvn | Move Not (aka not_bits) | mov -ve imm is standard |
| orr | Logical or_bits | or (unconditional) |
| rsb | Reverse Subtract | |
| rsc | Reverse Subtract with Carry | |
| sbc | Subtract with Carry | |
| smlal | Signed Long Multiply Accumulate | |
| smull | Signed Long Multiply | |
| stm | Store Multiple | push is standard |
| str | Store Register | mov [Rm|fp+k], Rn |
| sub | Subtract | |
| swi | Software Interrupt | svc (std), syscall (Phix only) |
| teq | Test Equivalence | |
| tst | Test | test (unconditional) |
Also, "lea Rn,[var]" is (usually) encoded as mov/orr (Phix-specific).
Pseudo-instructions
| Mnemonic | Description | Phix-specific and standard aliases |
| ASL | Arithmetic shift left (=mov) | lsl, shl |
| ASR | Arithmetic shift right (=mov) | |
| LEA | Load effective address (=mov/orr) | (Phix only) |
| LSL | Logical shift left (=mov) | shl, asl |
| LSR | Logical shift right (=mov) | shr |
| mov | (with memory address in a register) | ldr/str |
| ROR | Rotate | |
| neg | Negate | rsb |
The five main shift operations (asl/asr/lsl/lsr/ror) are just shorthands for the equivalent mov instruction with that operation embedded via the barrel shifter.
There is no difference whatsoever between asl and lsl, and in fact they use the same encoding.
Note that (the Phix-specific aliases) shl and shr must be unconditional, if used, ditto lea.
Registers
| r0-r10 | General purpose |
| fp | Frame pointer (not r11) |
| ip | Intra-proc (not particularly special) |
| sp | Stack pointer (not r13) |
| lr | Link register (not r14) |
| pc | Program counter (not r15) |
| s0-s31 | Single precision (32 bit) floats |
| d0-d15 | Double precision (64 bit) floats |
Phix does not support or permit the use of r11..r15 as (confusing) aliases for important registers.